Frequently Asked Question: "What is AC histogram testing?"
AC histogram testing is used to test analog-to-digital converters (ADCs) with the goal being to calculate the ADC's integral non-linearity (INL) and differential non-linearity (DNL). Note that AC histogram testing by itself cannot reliably calculate offset error or and gain error(s). An additional technique must be utilized to calculate those errors. For some mixed-signal devices, such as audio converters, offset error and gain error(s) are not all that critical.
Histogram testing works by applying a varying analog signal to the ADC's analog input. There are various approaches to AC histogram testing and the analog signal's amplitude can be slightly smaller than the ADC's analog input or slightly larger. If the amplitude is slightly smaller, then it should be small enough so that the ADC does not digitally clip at either negative full-scale or positive full-scale. If the amplitude is slightly larger, then the ADC's output should clip at both positive full-scale and negative full-scale.
The AC histogram test requires memory to store the number of occurrences of each digital code that the ADC produces. For example, if the ADC has a 16-bit resolution, then it can produce 65,536 (2^16) possible output codes: from code 0 to code 65,535 for an ADC whose output is encoded in a straight binary format. This memory must be able to store values that do not overflow the width of each memory location. Common memory word sizes are 16 bits or 32 bits. The memories word size can often dictate if the AC histogram testing uses an input amplitude that is slightly smaller than the ADC's input range or slightly larger. The reason is that the lowest possible output code and the highest possible output code may exceed a value of 2^16 for a 16-bit memory word size. Note that the lowest possible output code is not always code 0 (in straight binary format) or 65,535. The ADC may have "missing codes" near negative full-scale or positive full-scale.
When the AC histogram test starts, all memory locations are set to a value of 0. As the ADC produces each code, digital circuitry uses that code as an address into memory. The contents of that memory location are incremented by one. N number of conversions are performed over the course of the test. At the end of the test, the memory has a "histogram" of the number of occurrences of each possible digital output code. Note that this description does not have to occur exactly as indicated. It is perfectly acceptable to capture all of the ADC's digital results and process them after the test has ended.
The number of conversions, N, required in order to determine INL and DNL depends on the desired precision of the results. In addition, DNL is less sensitive to the number of conversions than INL. A value for N of 100,000 might give fairly decent DNL for a 12-bit converter but the INL results will be poor. A typical 12-bit ADC will require 1 million to 10 million conversions to give good, repeatable INL and DNL results. Likewise, 16-bit ADCs typically require at least 100 million conversions to give repeatable DNL and INL results.
In order for histogram testing to be considered "AC" histogram testing, the analog input should be a sine wave. The reason for using a sine wave is that it is relatively easy to produce a very linear, very low noise sine wave through the use of bandpass filters. Some AC histogram testing utilizes a low jitter square wave that is bandpass filtered to produce the sine wave. Histogram testing can also utilize a ramped voltage. The ramp is easy to produce at very low frequencies but is difficult or impossible to produce at higher frequencies. The advantage of the sine wave approach over the ramp approach is that INL and DNL can be determined more easily over a wider input frequency range.
In general, histogram testing is a great test technique. Ramp testing is often used on production test systems because it can give reasonable "production" test results in a short amount of time. AC histogram testing is also used extensively for very high-speed ADCs. collecting 10 million conversion results from a 100 MSPS ADC only takes 0.1 seconds. The main issue for histogram testing is that it does take a large number of conversions in order to get good, repeatable results suitable for debug, validation, and characterization. For a 16-bit, 100 kHz ADC, it might take at least 100 million conversions to calculate good INL and DNL and that require 1,000 seconds (almost 17 minutes) of time. A servo-loop test can actually take less time. Another issue with histogram testing is that the calculation of offset error and gain error requires a slightly different technique though it can sometimes use the same hardware.
As a final note, histogram testing is a "code center" test technique. This can be contrasted with an analog servo-loop or a digital servo-loop test which are "code edge" tests. Code edge testing finds the transition point between every two adjacent codes with a slowly changing, low-noise analog voltage and this takes time. Code center tests can have an advantage in that they can be faster than code edge tests for some ADCs (particularly high-speed ADCs). However, code center tests are not typically as repeatable as code edge tests. This is particularly true for high-resolution ADCs.