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Products - testQube 5220A - Parallel Data Collector

NOTE: this page discusses a product that is currently in development. Features and specifications listed here are subject to change.

The testQube 5220A parallel data collector can acquire up to 24 bits of DUT data at rates up to 250 MHz and up to 134 (2^27) million 30 bit results. It may be possible to acquire double data rate (DDR) data at rates up to 400 MHz but that functionality is still in development. In addition to the DUT data, the data collector can also acquire up to 30 additional bits of qualifier data. The sum of the DUT data bits plus the qualifier bits cannot exceed 30 bits total. For example, the collection of data from a 16-bit analog-to-digital converter (ADC) would leave 14-bits available as qualifiers.

Note that the DUT data values can be aligned in any manner within the 24-bit wide parallel data path but the data bits must be contiguous. A 16-bit value can be left aligned, right aligned, centered, least significant bit first, or most significant bit first. This flexibility is very useful for certain types of ADCs whose resolution can change or that support an optional sign bit under some modes of operation.

The qualifier bits can be used to identify data from the DUT versus other data that may be present in the data stream. For example, a multi-channel ADC may be configured to convert two or more channels for a "direct crosstalk test" (channel-to-channel in the analog domain) or a "residue crosstalk test" (the ADC has some sort of "memory" that causes a change in the next conversion result based on the previous result). In either case, a full-scale (relative to the ADC's input range) analog sine wave is applied to one channel of the ADC while a static analog voltage is applied to another. For this type of setup, the qualifier bits can be used, perhaps in conjunction with the pattern generator, to qualify which bits are collected. The data collector can be configured to collect only the data from the channel with the analog sine wave (perhaps for "AC" testing such as SNR, THD, etc.), from the channel with the static analog voltage (for either direct crosstalk or residue crosstalk), or from both channels.

The parallel data collector can acquire DUT data at frequencies below 25 MHz with no pipeline overhead. Very fast data collectors often require a large number of additional clock cycles after the last DUT data value in order to "push" the earlier data all the way to the data collector's memory. This overhead can create test issues for extremely slow speed devices such as ADCs operating below 1 kHz. The delay can also adversely impact test time in a variety of ways (depending on the type of testing being performed). For completely different reasons, there can be issues when storing data for extremely high-speed ADCs (operating in the gigahertz range). These devices often store the data locally, in memory located on the same die as the ADC, and then stream it out at a much slower rate. Since digital memory is almost always configured as a power of two, the data capture device would ideally allow exactly 2^N data values to be sent with no additional overhead. For example, a high-speed memory might capture 16,384 results from a 4 GHz ADC and then stream those results out much more slowly. For data rates of 25 MHz or less, the parallel data capture of the testQube 5220A can acquire and process DUT data with no additional clocks required. This allows a single data value from a 1 Hz ADC to be captured to memory with almost no delay overhead and 16,384 results from a multi-gigahertz ADC to be captured with no additional clocks necessary.

The parallel data collector can be configured to collect the very first data value from the DUT after power-up. The data collector has two distinct modes for data collection: data collection that is initiated immediately after power-up but before the DUT has started operating and data collection that is initiated while the DUT is operating. Capturing the very first data value can be critical for some ADCs, particularly very slow ADCs. However, in order to use the "capture first" data capture mode, the user must be certain the DUT will not be producing data when data capture is enabled.

The overall data collector, in both its serial and parallel modes, has a feature that allows a synchronization signal to be provided to the data collector. This optional signal is used in those cases where there is a discontinuity or "gap" in the data provided by the DUT to the data collector. The simplest case of this is when a microcontroller has a high-speed embedded ADC and the microcontroller cannot provide continuous data beyond a certain number of conversion results. For example, the microcontroller might be able to provide 8,192 contiguous samples but then there will be a delay of one or more conversion results from the ADC (perhaps because the microcontroller program has to loop from the end back to the beginning). In these cases, the discontinuity will make certain types of testing impossible on a repeatable basis. The solution is to allow the microcontroller to signal the data collector that a contiguous group of results is starting or about to start. For this purpose, the data collector provides two "start of contiguous data" inputs that can be utilized with these test situations. The user can define how many data acquisitions to ignore (or throw away) after the start of contiguous data signal occurs so this signal does not have to be precisely aligned to the start of valid data.

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