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Products - testQube 5220A - Serial Data Collector

NOTE: this page discusses a product that is currently in development. Features and specifications listed here are subject to change.

The testQube 5220A serial data collector can acquire up to 96 bits of DUT data and qualifiers at serial clock rates up to 100 MHz, parallel data rates up to 25 MHz, and up to 134 (2^27) million 32-bit results, 64 (2^26) million 64-bit results, and 44.7 million 96-bit results. Serial data bit widths can be 1, 2, 4, or 8 bits (also called "lanes"). A discussion about serial data streams can quickly become confusing so the previous statements are broken down in the following paragraphs.

The testQube 5220A's serial data capture mode is layered on top of the parallel data capture engine but with some additional features to handle issues unique to mixed-signal devices that utilize a serial interface. The capture of data from a serial device makes use of a serial-to-parallel converter. This is simply a shift register and it has a maximum width of 80 bits. At some point, the data in the shift register is latched into a set of parallel flip-flops and the serial data is now parallel data. If you have not read the information on the testQube 5220A's parallel data capture, you might want to do so at this point. It might aid in making the following discussion more understandable.

Serial interfaces are broadly categorized into two sets: those with a latch enable signal that is independent of the serial clock (effectively asynchronous to the clock) or those that have a frame synchronization signal that is synchronous to the clock (valid on the same clock edge as the data is valid). In fact, the term "latch enable" is often associated with shift registers where the latch enable signal causes the shift register to latch its current state into a parallel array of flip-flops. The latch enable signal can perform this action even in the absence of any serial clock activity. The term "frame synchronization" (or "frame sync" for short) is more often associated with a signal that is synchronous to the clock and "frames" the data within the serial data stream. The frame synchronization signal is only valid when referenced to one edge of the serial clock. The serial data collector supports both asynchronous and synchronous latch enable / frame sync signals. In addition, it supports either or both frame synchronization edges, a positive-going latch enable signal, a negative-going latch enable signal, or both. The latch enable (or frame sync) signal is not restricted in placement relative to the data being latched but must occur within a few hundred serial clocks prior to the last bit in the data stream. This is a good place to note that the serial data can be least significant bit first or most significant bit first. In addition, the data of interest must be contiguous. Within the serial word, the data can span any contiguous position.

There are currently two serial-to-parallel converters implemented in each 30 bit data collector. This is done for various reasons that aren't critical to this discussion and the final design might implement only one of the two. The point here is that each serial-to-parallel converter has access to one of two latch enable (or frame synchronization) signals and up to 8 serial data bits (or lanes). There are additional bits which can be used as qualifiers and also "start of contiguous data" signals. It should be pointed out that the testQube software only supports a maximum data width for DUT data of up to 40 bits within the 80 bit serial word.

The serial-to-parallel converter has four shift modes: 1-bit, 2-bit, 4-bit, and 8-bit. These support the serial data widths of 1 bit, 2 bits, 4 bits, and 8 bits. The shift register also has three additional "entry points" for the shift register. These are located at bit position 20, 40, and 60. This allows the shift register to support up to 8 lanes of serial data or up to four independent serial results up to 20 bits in length (or two serial results up to 40 bits in length). This flexibility supports a wide variety of serial interfaces.

When the 80 bits from the serial shift register are latched, they are also latched with an additional 16 bits of parallel qualifier data. There is a maximum of 16 bits of parallel qualifier data and some of the data inputs will be used for the latch enable signal, the start-of-contiguous data signal, and one or more data bits (the serial clock is provided on a dedicated clock pin that is not part of the data collector's 30 inputs bits). The sum of the qualifier bits and all signals related to the serial interface (not including the serial clock) cannot exceed 16. Note that inclusion of the latch enable (frame sync) signal allows the user to configure the qualifier bits in such a way that "left" or "right" data can be identified (this is often the case for stereo audio analog-to-digital converters [ADCs]).

The ultimate result of the 80-bit shift register word plus the 16 bits of qualifier data is a 96-bit word. Obviously, all 96 bits of the word are not going to be of interest. However, the result contains some combination of data, qualifiers, and additional information that is part of the serial interface format to and from the DUT. This additional information might be configuration data going to the DUT just after power-up. That information can be acquired by the data collector and ultimately saved by the PC software so that the DUT's configuration is available within the file itself. The additional information might also identify which channel was selected for the conversion by the ADC. While there are 80 bits from the serial-to-parallel converter and 16 bits that are parallel qualifiers, any of the 96 bits of the resulting word can actually serve as qualifiers.

The qualifier bits can be used to identify data from the DUT versus other data that may be present in the data stream. For example, a multi-channel ADC may be configured to convert two or more channels for a "direct crosstalk test" (channel-to-channel in the analog domain) or a "residue crosstalk test" (the ADC has some sort of "memory" that causes a change in the next conversion result based on the previous result). In either case, a full-scale (relative to the ADC's input range) analog sine wave is applied to one channel of the ADC while a static analog voltage is applied to another. For this type of setup, the qualifier bits can be used, perhaps in conjunction with the pattern generator, to qualify which bits are collected. The data collector can be configured to collect only the data from the channel with the analog sine wave (perhaps for "AC" testing such as SNR, THD, etc.), from the channel with the static analog voltage (for either direct crosstalk or residue crosstalk), or from both channels (for post-processing outside the domain of the testQube 5220A).

The data collector's serial-to-parallel converter can generate parallel data at frequencies up to 25 MHz. Within the data collector, there is no pipeline overhead after the serial word is latched into the collector's parallel registers. Serial data collectors sometimes require a few additional clock cycles after the last DUT data value in order to "push" the earlier data all the way to the data collector's memory. This overhead can create test issues for extremely slow speed devices such as ADCs operating below 1 kHz. The delay can also adversely impact test time in a variety of ways (depending on the type of testing being performed).

The serial data collector can be configured to collect the very first data value from the DUT after power-up. The data collector has two distinct modes for data collection: data collection that is initiated immediately after power-up but before the DUT has started operating and data collection that is initiated while the DUT is operating. Capturing the very first data value can be very important for some ADCs, particularly very slow ADCs. However, in order to use the "capture first" data capture mode, the user must be certain the DUT will not be producing data when data capture is enabled.

The overall data collector, in both its serial and parallel modes, has a feature that allows a synchronization signal to be provided to the data collector. This optional signal is used in those cases where there is a discontinuity or "gap" in the data provided by the DUT to the data collector. The simplest case of this is when a microcontroller has a high-speed embedded ADC and the microcontroller cannot provide continuous data beyond a certain number of conversion results. For example, the microcontroller might be able to provide 8,192 contiguous samples but then there will be a delay of one or more conversion results from the ADC (perhaps because the microcontroller program has to loop from the end back to the beginning). In these cases, the discontinuity will make certain types of testing impossible on a repeatable basis. The solution is to allow the microcontroller to signal the data collector that a contiguous group of results is starting or about to start. For this purpose, the data collector provides two "start of contiguous data" inputs that can be utilized with these test situations. The user can define how many data acquisitions to ignore (or throw away) after the start of contiguous data signal occurs so this signal does not have to be precisely aligned to the start of valid data.

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