NOTE: this product is currently in development and specifications listed here are subject to change.
The testQube 5220A pattern generator provides digital stimulus to the device under test (DUT) and other circuitry on the test head. The digital stimulus is defined in a text file created and specified by the user. The testQube 5220A PC software supports the same file format as that used for the ATS4000's ARM6444 daughtercard. It also supports an extended format that can greatly reduce the length of the file and shorten the time required to create it. Nested looping constructs are now supported along with embedded data variables. The data variables can be specified at the beginning of the pattern file and referenced anywhere within the file. This greatly improves the readability of the file and the variables can also be specified from within the PC software without modifying the pattern file itself. This allows automation scripting to modify the variables without having to change the pattern file itself. This feature can also be used for digital-to-analog converter (DAC) testing.
A pattern is typically comprised of two sections: an initial section that is produced just once and a second section that loops as long as the pattern generator is enabled. The initial section is used to configure the DUT's internal registers. Once configured, the DUT should not need to be re-configured unless it is reset or power is cycled. So, this section of the pattern appears only after power is first applied to the DUT. The user can specify that the initial section is to be repeated every time data collection is initiated. The second section of the pattern continuously repeats and causes the DUT to perform a repetitive action. For an analog-to-digital converter (ADC), this action is converting an analog input to a digital value. The repeating or "looping" section of the pattern can be any length from a single pattern to the limit of pattern memory. There is no discontinuity (time penalty) when the pattern steps from the last pattern in the loop to the first.
The width of the pattern generator is up to 30 parallel bits. Each individual bit can be defined by the user to be either static high, static low, defined by the pattern file, or dynamically toggling between high and low in synchronization with the pattern generator clock (high or low when the pattern generator clock is low and the opposite when it is high). The number of patterns can be up to 537 (2^29) million for patterns of width up to 8 bits, 268 (2^28) million for patterns of width up to 16 bits, and 134 (2^27) million for patterns of width up to 30 bits.
The maximum frequency of the pattern generator is 250 MHz though a double data rate (DDR) mode may be available that will provide a maximum frequency up to 400 MHz. In single data rate (SDR) mode, the edge placement can be defined by the user such that the chosen digital signals will be one half a clock period behind the other digital channels. This provides edge placement resolution of 2 ns when operating at 250 MHz.
The testQube 5220A can provide up to 8 pattern generators to a single DUT or up to two for each of four DUTs. Typically, a single pattern generator is used to produce the digital signals that will stimulate the DUT. For an ADC, X number of patterns will cause it to produce a single digital result. X can be any number within a reasonable limit. For example, if X is 0.01, this would typically indicate that the ADC contains a phase locked loop that is multiplying an external digital clock input to create a much higher frequency clock internal to the ADC. In this case, every pattern would generate 100 digital results. X might also have a value of 20. That would indicate that 20 patterns are required in order to produce a single digital result from the ADC.
The digital pattern could also stimulate a DAC. In that case, the analog output of the DAC is of interest and that can be measured by Digital Voltmeters (DVMs) internal to the testQube or by external DVMs. The pattern file can contain data variables that can be identified to the PC software so that the software can modify the DAC setting. By doing this, the transfer function of the DAC can be fully tested. The pattern generator also has a data generator feature that can be used to generate dynamic digital data that is embedded within the pattern on-the-fly. This data can be arbitrary data stored in memory or waveform data produced via an numerically controlled oscillator (NCO) and, optionally, a phase-to-sine converter (PSC). The data generator feature is used for dynamic DAC testing such as sine generation (SNR, THD, etc.), step response, settling time, and glitch energy (note that some of these tests may require additional testQube 5220A internal modules or external test equipment such as oscilloscope and spectrum analyzers depending on the speed of the DAC being tested).
The pattern file can also operate other circuitry on the test head. For example, it might be desirable to create a special test where a high-speed DAC is used to generate an analog waveform in order to test an ADC. In this case, one pattern file might be used to operate the DAC while a second is used to operate the ADC.
For ADC testing, keep in mind that the pattern file not only configures and stimulates the DUT but can also be used to determine what DUT data is collected by the data collector. For example, a multi-channel ADC might be configured to digitize one channel and then another but only data from one of the two channels is to be collected. By feeding back some of the signals from the pattern generator to the data collector, this selection can be easily changed. The point here is that much more complex arrangements between the pattern generator(s) and data collector(s) are possible but beyond the scope of this simple overview.